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1/19 may 2002 m48z58 m48z58y 5.0v, 64 kbit (8 kbit x 8) zeropower ? sram features summary n integrated, ultra low power sram, power-fail control circuit, and battery n read cycle time equals write cycle time n automatic power-fail chip deselect and write protection n write protect voltages: (v pfd = power-fail deselect voltage) C m48z58: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v C m48z58y: 4.5 to 5.5v 4.2v v pfd 4.5v n self-contained battery in the caphat? dip package n packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) n soic package provides direct connection for a snaphat top which contains the battery n pin and function compatible with jedec standard 8k x 8 srams figure 1. caphat? dip solution figure 2. soic solution pcdip28 (pc) battery caphat 28 1 snaphat (sh) battery soh28 (mh) 28 1
m48z58, m48z58y 2/19 table of contents description ....................................................................3 logicdiagram(figure3.).........................................................3 signalnames(table1.)..........................................................3 dip connections (figure 4.) .......................................................4 soic connections (figure 5.) ......................................................4 blockdiagram(figure6.).........................................................4 maximumrating.................................................................5 absolutemaximumratings(table2.) ...............................................5 dc and ac parameters. . ........................................................6 operating and ac measurement conditions (table 3.) ..................................6 acmeasurementloadcircuit(figure7.).............................................6 capacitance (table 4.) . . . ........................................................6 dccharacteristics(table5.) ......................................................7 operatingmodes...............................................................7 operating modes (table 6.) ........................................................7 readmode....................................................................8 readmodeacwaveforms(figure8.)..............................................8 readmodeaccharacteristics(table7.)............................................8 writemode...................................................................9 write enable controlled, write mode ac waveforms (figure 9.) ........................9 chipenablecontrolled,writemodeacwaveforms(figure10.).........................9 writemodeaccharacteristics(table8.) ..........................................10 dataretentionmode............................................................11 powerdown/upmodeacwaveforms(figure11.) ....................................11 powerdown/upaccharacteristics(table9.)........................................11 powerdown/uptrippointsdccharacteristics(table10.)..............................12 v cc noise and negative going transients . ..........................................12 supplyvoltageprotection(figure12.)..............................................12 partnumbering ...............................................................13 snaphatbatterytable(table12.)................................................13 package mechanical information . . . ..........................................14 revisionhistory...............................................................18
3/19 m48z58, m48z58y description the m48z58/y zeropower ? ram is an 8k x 8 non-volatile static ram that integrates power-fail deselect circuitry and battery control logic on a sin- gle die. the monolithic chip is available in two spe- cial packages to provide a highly integrated battery backed-up memory solution. the m48z58/y is a non-volatile pin and function equivalent to any jedec standard 8k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600mil dip caphat? houses the m48z58/y silicon with a long life lithium button cell in a single package. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped sep- arately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery package (e.g., snaphat) part number is m4z28-br00sh (see table 12, page 13). figure 3. logic diagram table 1. signal names ai01176b 13 a0-a12 w dq0-dq7 v cc m48z58 m48z58y g v ss 8 e a0-a12 address inputs dq0-dq7 data inputs / outputs e chip enable input g output enable input w write enable input v cc supply voltage v ss ground nc not connected internally
m48z58, m48z58y 4/19 figure 4. dip connections figure 5. soic connections figure 6. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 nc a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 nc v cc ai01177b m48z58 m48z58y 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 ai01178b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 nc a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 nc v cc m48z58y ai01394 lithium cell v pfd v cc v ss voltage sense and switching circuitry 8k x 8 sram array a0-a12 dq0-dq7 e w g power
5/19 m48z58, m48z58y maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 C40 to 85 c t stg storage temperature (v cc off, oscillator off) snaphat ? C40 to 85 c soic C55 to 125 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7.0 v v cc supply voltage C0.3 to 7.0 v i o output current 20 ma p d power dissipation 1 w
m48z58, m48z58y 6/19 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac measurement load circuit table 4. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48z58 m48z58y unit supply voltage (v cc ) 4.75 to 5.5v 4.5 to 5.5 v ambient operating temperature (t a ) grade 1 0 to 70 0 to 70 c grade 6 C40 to 85 C40 to 85 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai01030 5v out c l = 100pf or 5pf c l includes jig capacitance 1.9k w device under test 1k w symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
7/19 m48z58, m48z58y table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. outputs deselected. 3. negative spikes of C1v allowed for up to 10ns once per cycle. operating modes the m48z58/y also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condi- tion. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc .asv cc falls be- low battery switchover voltage (v so ), the control circuitry connects the battery which maintains data until valid power returns. table 6. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage. 1. see table 10, page 12 for details. symbol parameter test condition (1) min max unit i li input leakage current 0v v in v cc 1 a i lo (2) output leakage current 0v v out v cc 1 a i cc supply current outputs open 50 ma i cc1 supply current (standby) ttl e =v ih 3ma i cc2 supply current (standby) cmos e =v cc C 0.2v 3ma v il (3) input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
m48z58, m48z58y 8/19 read mode the m48z58/y is in the read mode whenever w (write enable) is high, e (chip enable) is low. thus, the unique address specified by the 13 ad- dress inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be avail- able at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv )oroutput enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 8. read mode ac waveforms note: write enable (w )=high. table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. c l = 5pf (see figure 7, page 6). symbol parameter (1) m48z58/y unit min max t avav read cycle time 70 ns t av qv address valid to output valid 70 ns t elqv chip enable low to output valid 70 ns t glqv output enable low to output valid 35 ns t elqx (2) chip enable low to output transition 5 ns t glqx (2) output enable low to output transition 5 ns t ehqz (2) chip enable high to output hi-z 25 ns t ghqz (2) output enable high to output hi-z 25 ns t axqx address transition to output transition 10 ns ai01385 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a12 e g dq0-dq7 valid
9/19 m48z58, m48z58y write mode the m48z58/y is in the write mode whenever w and e are low. the start of a write is referenced from the latter occurring falling edge of w or e .a write is terminated by the earlier rising edge of w or e . the addresses must be held valid through- out the cycle. e or w must return high for a mini- mum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t d- vwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g ,alowonw will disable the outputs t wlqz after w falls. figure 9. write enable controlled, write mode ac waveforms figure 10. chip enable controlled, write mode ac waveforms ai01386 tavav twhax tdvwh data input a0-a12 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01387b tavav tehax tdveh a0-a12 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
m48z58, m48z58y 10/19 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. c l = 5pf (see figure 7, page 6). 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48z58/y unit min max t avav write cycle time 70 ns t avwl address valid to write enable low 0 ns t avel address valid to chip enable low 0 ns t wlwh write enable pulse width 50 ns t eleh chip enable low to chip enable high 55 ns t whax write enable high to address transition 0 ns t ehax chip enable high to address transition 0 ns t dvwh input valid to write enable high 30 ns t dveh input valid to chip enable high 30 ns t whdx write enable high to input transition 5 ns t ehdx chip enable high to input transition 5 ns t wlqz (2,3) write enable low to output hi-z 25 ns t av wh address valid to write enable high 60 ns t av eh address valid to chip enable high 60 ns t whqx (2,3) write enable high to output transition 5 ns
11/19 m48z58, m48z58y data retention mode with valid v cc applied, the m48z58/y operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will automati- cally power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z58/y may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data. the internal button cell will maintain data in the m48z58/y for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc .normalram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012. figure 11. power down/up mode ac waveforms table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. t rec (min) = 20ms for industrial temperature grade (6) device. symbol parameter (1) min max unit t pd e or w at v ih before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec (4) v pfd (max) to inputs recognized 40 200 ms ai01168c v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec
m48z58, m48z58y 12/19 table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 3. at 25c. v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (see figure 12) is recommended in order to provide the needed fil- tering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky diode from v cc to v ss (cathode con- nected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount). figure 12. supply voltage protection symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48z58 4.5 4.6 4.75 v m48z58y 4.2 4.35 4.5 v v so battery back-up switchover voltage 3.0 v t dr (3) expected data retention time 10 years ai02169 v cc 0.1 m f device v cc v ss
13/19 m48z58, m48z58y part numbering table 11. ordering information scheme note: 1. the m48z58 part is offered with the pcdip28 (i.e. caphat) package only. 2. the soic package (soh28) requires the battery package (snaphat ? ) which is ordered separately under the part number m4zxx-br00sh in plastic tube or m4zxx-br00shtr in tape & reel form. 3. industrial temperature grade available in soic package (soh28) only. caution : do not place the snaphat battery package m4zxx-br00sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 12. snaphat battery table example: m48z 58y C70 mh 1 tr device type m48z supply voltage and write protect voltage 58 (1) =v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 58y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v speed C70 = 70ns (for m48z58/y) package pc = pcdip28 mh (2) = soh28 temperature range 1 = 0 to 70c 6 (3) = C40 to 85c shipping method for soic blank = tubes tr = tape & reel part number description package m4z28-br00sh lithium battery (48mah) snaphat sh m4z32-br00sh lithium battery (120mah) snaphat sh
m48z58, m48z58y 14/19 package mechanical information figure 13. pcdip28 C 28-pin plastic dip, battery caphat?, package outline note: drawing is not to scale. table 13. pmdip28 C 28-pin plastic dip, battery caphat?, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
15/19 m48z58, m48z58y figure 14. soh28 C 28-lead plastic small outline, battery snaphat, package outline note: drawing is not to scale. table 14. soh28 C 28-lead plastic small outline, battery snaphat, package mechanical data symbol mm inch typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
m48z58, m48z58y 16/19 figure 15. sh C 4-pin snaphat housing for 48mah battery, package outline note: drawing is not to scale. table 15. sh C 4-pin snaphat housing for 48mah battery, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
17/19 m48z58, m48z58y figure 16. sh C4-pin snaphat housing for 120mah battery, package outline note: drawing is not to scale. table 16. sh C 4-pin snaphat housing for 120mah battery, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
m48z58, m48z58y 18/19 revision history table 17. revision history date revision details march 1999 first issue 02/10/00 2-socket soh and 2-pin sh packages removed 02/22/00 data retention mode paragraph changed 09/14/01 reformatted; added temperature information (table 4, 5, 7, 8, 9, 10) 05/29/02 modify reflow time and temperature footnotes (table 2)
19/19 m48z58, m48z58y information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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